1. Field of the Invention
This invention relates to an alignment strategy of alignment marks, and more particularly, to corrections for shifts of alignment marks.
2. Description of Related Art
Nearly all very-large-scale-integration (VLSI) and ultra-large-scale-integration (ULSI) circuits are made with multilevel metallization. It provides greater flexibility in circuit design. As more and more layers are added in an integrated circuit (IC) process, planarization of the IC topography in intermediate steps is required. This is because non-planar surfaces interfere with the optical resolution of subsequent photolithography steps.
One way to planarize the IC topography is to use a global planarization techniques such as chemical-mechanical polishing (CMP). A problem with the CMP is that it often makes the step heights too shallow in situations where the step heights are alignment marks used in the subsequent photolithography steps. Fortunately, solutions to this problem such as a clearout window method and an alignment mark segment have been already proposed.
However. there is still another problem with the CMP used in the IC topography planarization. For example, the mechanical polishing of the CMP process alters the location of the alignment marks. Thus the alignment marks, as detected by an optical alignment system, can lead to errors. These errors cause photolithography misalignments if they are not corrected.